Move bounce buffer impl into the esp-hal-bounce-buffers crate
This commit is contained in:
Jakub Hlusička
parent
07efc876f3
commit
3b291669ca
11
firmware/Cargo.lock
generated
11
firmware/Cargo.lock
generated
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@ -30,6 +30,7 @@ dependencies = [
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"esp-backtrace",
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"esp-bootloader-esp-idf",
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"esp-hal",
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"esp-hal-bounce-buffers",
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"esp-metadata-generated 0.3.0 (registry+https://github.com/rust-lang/crates.io-index)",
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"esp-println",
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"esp-radio",
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@ -2143,6 +2144,15 @@ dependencies = [
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"xtensa-lx-rt",
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]
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[[package]]
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name = "esp-hal-bounce-buffers"
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version = "0.1.0"
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dependencies = [
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"document-features",
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"esp-hal",
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"ouroboros",
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]
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[[package]]
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name = "esp-hal-procmacros"
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version = "0.21.0"
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@ -6875,6 +6885,7 @@ checksum = "a0f368519fc6c85fc1afdb769fb5a51123f6158013e143656e25a3485a0d401c"
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[[package]]
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name = "spectre-api-sys"
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version = "0.1.0"
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source = "git+c:/Users/Limeth/workspace/rust/spectre-api-sys#9e844eb056c3dfee8286ac21ec40fa689a8b8aa2"
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dependencies = [
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"bindgen",
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"cc",
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@ -87,6 +87,7 @@ esp-metadata-generated = { version = "0.3.0", features = ["esp32s3"] }
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hex = { version = "0.4.3", default-features = false, features = ["alloc"] }
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indoc = "2.0.7"
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ouroboros = "0.18.5"
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esp-hal-bounce-buffers = { git = "https://forgejo.limeth.cz/limeth/esp-hal-bounce-buffers", features = ["esp32s3"] }
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# A fork of slint with patches for `allocator_api` support.
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# Don't forget to change `slint-build` in build dependencies, if this is changed.
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@ -37,9 +37,7 @@ use embassy_time::{Duration, Timer};
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use esp_alloc::{HeapRegion, MemoryCapability};
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use esp_bootloader_esp_idf::partitions::PartitionTable;
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use esp_hal::clock::CpuClock;
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use esp_hal::dma::{
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BurstConfig, ExternalBurstConfig, InternalBurstConfig,
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};
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use esp_hal::dma::{BurstConfig, ExternalBurstConfig, InternalBurstConfig};
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use esp_hal::efuse::Efuse;
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#[cfg(not(feature = "alt-log"))]
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use esp_hal::gpio::NoPin;
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@ -59,6 +57,7 @@ use esp_hal::system::Stack;
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use esp_hal::timer::timg::TimerGroup;
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use esp_hal::uart::{Uart, UartRx};
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use esp_hal::{Blocking, interrupt};
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use esp_hal_bounce_buffers::{DmaBounce, Swapchain, allocate_dma_buffer_in};
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use esp_rtos::embassy::{Executor, InterruptExecutor};
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use esp_storage::FlashStorage;
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use i_slint_core::software_renderer::TargetPixel;
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@ -85,7 +84,7 @@ use crate::matrix::IoeMatrix;
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use crate::peripherals::st7701s::St7701s;
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use crate::proxy::create_hid_report_interceptor;
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use crate::ui::backend::SlintBackend;
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use crate::ui::dpi::{DmaBounce, Framebuffer, Swapchain, allocate_dma_buffer_in};
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use crate::ui::dpi::Framebuffer;
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use crate::vial::{
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CustomKeycodes, VIAL_KEYBOARD_DEF, VIAL_KEYBOARD_ID, VIAL_KEYBOARD_NAME, VIAL_PRODUCT_ID,
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VIAL_VENDOR_ID,
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@ -192,7 +191,7 @@ async fn test_bounce_buffers(
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{
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let write_guard = &mut swapchain_writer.write();
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let buffer_src = write_guard.cast::<Rgb565Pixel>();
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let buffer_src = bytemuck::cast_slice_mut::<u8, Rgb565Pixel>(write_guard);
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let colors = (0..WIDTH_VISIBLE_PIXELS as u8 / 2)
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.rev()
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.map(|val| Rgb565Pixel::from_rgb(0xFF, val * 2, 0))
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@ -231,7 +230,7 @@ async fn test_bounce_buffers(
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burst_config,
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true,
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);
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buf.launch_interrupt_driven_task().await;
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buf.launch_interrupt_driven_task();
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error!("TEST BOUNCE BUFFERS SECTION DONE");
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}
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@ -771,8 +770,7 @@ async fn main_task(peripherals: MainPeripherals) {
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.bounce_buffers
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.take()
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.unwrap()
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.launch_interrupt_driven_task()
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.await;
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.launch_interrupt_driven_task();
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// TODO: Probably want to select! instead and re-try.
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join_all![
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@ -9,6 +9,7 @@ use alloc::{
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};
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use critical_section::Mutex;
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use esp_hal::time::Instant;
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use esp_hal_bounce_buffers::SwapchainWriter;
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use log::{debug, info};
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use slint::{
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EventLoopError, PhysicalSize, SharedString, WindowSize,
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@ -19,10 +20,7 @@ use slint::{
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};
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use xkbcommon::xkb::{self, Keysym};
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use crate::{
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proxy::{KEY_MESSAGE_CHANNEL, TryFromKeysym},
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ui::dpi::SwapchainWriter,
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};
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use crate::proxy::{KEY_MESSAGE_CHANNEL, TryFromKeysym};
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use super::window_adapter::SoftwareWindowAdapter;
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@ -135,7 +133,7 @@ impl slint::platform::Platform for SlintBackend {
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// TODO: VSYNC support.
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let mut swapchain = self.swapchain.borrow_mut();
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let mut write_guard = swapchain.write();
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let framebuffer = write_guard.cast::<Rgb565Pixel>();
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let framebuffer = bytemuck::cast_slice_mut::<u8, Rgb565Pixel>(&mut write_guard);
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renderer.render(framebuffer, self.window_size[1] as usize);
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info!("UI rendered.");
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});
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@ -25,6 +25,7 @@ use esp_hal::{
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ram,
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spi::master::AnySpi,
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};
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use esp_hal_bounce_buffers::{DmaBounce, Swapchain, SwapchainWriter, allocate_dma_buffer_in};
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use log::error;
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use ouroboros::self_referencing;
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@ -61,894 +62,6 @@ pub unsafe fn cache_invalidate_addr(addr: u32, size: u32) {
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}
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}
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// const DMA_CHANNEL_INBOUND: usize = 0;
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// const INTERRUPT_INBOUND: Interrupt = Interrupt::DMA_IN_CH0;
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const DMA_CHANNEL_OUTBOUND: usize = 2;
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const INTERRUPT_OUTBOUND: Interrupt = Interrupt::DMA_OUT_CH2;
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#[self_referencing]
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struct ReceivingTransfer {
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mem2mem: SimpleMem2Mem<'static, Blocking>,
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#[borrows(mut mem2mem)]
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#[covariant]
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transfer: Option<SimpleMem2MemTransfer<'this, 'static, Blocking>>,
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}
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pub struct Swapchain {
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pub framebuffers: [&'static mut [u8]; 2],
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}
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impl Swapchain {
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pub fn into_reader_writer(self) -> (SwapchainReader, SwapchainWriter) {
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assert_eq!(
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self.framebuffers[0].len(),
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self.framebuffers[1].len(),
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"framebuffers in a swapchain must have an equal length"
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);
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let reader_index = Arc::new(AtomicBool::new(true));
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(
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SwapchainReader {
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framebuffers_rw: [
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self.framebuffers[0] as *const [u8],
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self.framebuffers[1] as *const [u8],
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],
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reader_index: reader_index.clone(),
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},
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SwapchainWriter {
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framebuffers_wr: [
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self.framebuffers[1] as *mut [u8],
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self.framebuffers[0] as *mut [u8],
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],
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reader_index,
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},
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)
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}
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}
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// TODO: Don't need to store the framebuffer length twice. Use `*const u8` instead, and store length separately.
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pub struct SwapchainReader {
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/// These are in the opposite order to `SwapchainWriter`'s framebuffers.
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framebuffers_rw: [*const [u8]; 2],
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reader_index: Arc<AtomicBool>,
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}
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unsafe impl Send for SwapchainReader {}
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impl SwapchainReader {
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fn len(&self) -> usize {
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self.framebuffers_rw[0].len()
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}
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fn load_read_index(&self) -> usize {
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self.reader_index.load(atomic::Ordering::SeqCst) as usize
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}
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fn get_latest_framebuffer(&self) -> &[u8] {
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unsafe { &*self.framebuffers_rw[self.load_read_index()] }
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}
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}
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// TODO: Don't need to store the framebuffer length twice. Use `*mut u8` instead, and store length separately.
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pub struct SwapchainWriter {
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/// These are in the opposite order to `SwapchainReader`'s framebuffers.
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framebuffers_wr: [*mut [u8]; 2],
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reader_index: Arc<AtomicBool>,
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}
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unsafe impl Send for SwapchainWriter {}
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impl SwapchainWriter {
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fn len(&self) -> usize {
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self.framebuffers_wr[0].len()
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}
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pub fn write(&mut self) -> SwapchainWriteGuard<'_> {
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let framebuffer_ptr =
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self.framebuffers_wr[self.reader_index.load(atomic::Ordering::SeqCst) as usize];
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SwapchainWriteGuard {
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framebuffer: unsafe { &mut *framebuffer_ptr },
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reader_index: &self.reader_index,
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}
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}
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}
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pub struct SwapchainWriteGuard<'a> {
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framebuffer: &'a mut [u8],
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reader_index: &'a AtomicBool,
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}
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impl<'a> SwapchainWriteGuard<'a> {
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pub fn cast<T: NoUninit + AnyBitPattern>(&mut self) -> &mut [T] {
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bytemuck::cast_slice_mut::<_, T>(self.framebuffer)
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}
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}
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impl Drop for SwapchainWriteGuard<'_> {
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fn drop(&mut self) {
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self.reader_index.fetch_xor(true, atomic::Ordering::SeqCst);
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}
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}
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impl<'a> Deref for SwapchainWriteGuard<'a> {
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type Target = [u8];
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fn deref(&self) -> &Self::Target {
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self.framebuffer
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}
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}
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impl<'a> DerefMut for SwapchainWriteGuard<'a> {
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fn deref_mut(&mut self) -> &mut Self::Target {
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self.framebuffer
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}
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}
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pub struct DmaBounce {
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// TODO: Make these generic.
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// They currently cannot be generic, because they lacks a `reborrow` method.
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channel: DMA_CH0<'static>,
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// This can also be more generic, see `DmaEligible` in `Mem2Mem::new`.
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peripheral_src: AnySpi<'static>,
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// This can also be more generic, see `DmaEligible` in `Mem2Mem::new`.
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peripheral_dst: Option<Dpi<'static, Blocking>>,
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// TODO: Combine with peripheral_dst using an enum?
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transfer_dst: Option<DpiTransfer<'static, DmaTxBounceBuf, Blocking>>,
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// TODO: Consider having a separate burst config for the two transfers.
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burst_config: BurstConfig,
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cyclic: bool,
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/// The size of each window.
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window_size: usize,
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/// The number of windows.
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windows_len: usize,
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swapchain_src: SwapchainReader,
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// Two buffers of size `window_size`,
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// one of which is being written to, while the other is being read from.
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bounce_buffer_dst: &'static mut [u8],
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bounce_buffer_src: &'static mut [u8],
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// A descriptor list that spans a buffer of size `window_size`.
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// The buffer pointers need to be updated before each transmission to point to the correct window in the source buffer `src_buffer`.
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src_descs: &'static mut [DmaDescriptor],
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// A descriptor list that spans a buffer of size `window_size`.
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// The buffer pointers need to be updated before each transmission to point to the correct bounce buffer.
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bounce_dst_descs: &'static mut [DmaDescriptor],
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// A cyclic descriptor list that spans the buffers `bounce_buffer_dst` and `bounce_buffer_src`.
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bounce_src_descs: &'static mut [DmaDescriptor],
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descriptors_per_window: usize,
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// The index of the next window about to be received into the destination bounce buffer.
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window_index_next: usize,
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frame_index_next: usize,
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receiving_transfer: Option<ReceivingTransfer>,
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}
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impl DmaBounce {
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/// * `allocator` - The allocator used to allocate the bounce buffers.
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/// * `channel` - The DMA channel used to transfer data from the source buffer to the bounce buffers.
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/// * `peripheral_src` - The peripheral to transfer data from the source buffer to the bounce buffers.
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/// * `peripheral_dst` - The peripheral to transfer data to, from the bounce buffers.
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/// * `buffer_src` - The source buffer, typically allocated in external memory.
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/// * `row_front_porch_bytes` - The number of arbitrary-valued bytes to be sent in front of each row to the destination peripheral.
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/// * `row_width_bytes` - The width of a row, in bytes.
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/// * `window_size_rows` - The size of a single bounce buffer, in rows.
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/// * `burst_config` - The burst config to use for memory transfers (both in and out). TODO: This could be split.
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/// * `cyclic` - Experimental! Whether to use a cyclic descriptor list for transfer from the bounce buffers to the destination peripheral.
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pub fn new(
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allocator: impl Allocator + Copy + 'static,
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channel: DMA_CH0<'static>,
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peripheral_src: AnySpi<'static>,
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peripheral_dst: Dpi<'static, Blocking>,
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swapchain_src: SwapchainReader,
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row_front_porch_bytes: usize,
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row_width_bytes: usize,
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window_size_rows: usize,
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burst_config: BurstConfig,
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cyclic: bool,
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) -> Self {
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let window_size = row_width_bytes * window_size_rows;
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assert_eq!(
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swapchain_src.len() % window_size,
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0,
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"the size of a source buffer must be a multiple of the window size ({window_size} bytes), but it is {len} bytes large",
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len = swapchain_src.len()
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);
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// Conservative alignment. Maxiumum of the cartesian product of [tx, rx] × [internal, external].
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let alignment = burst_config.min_compatible_alignment();
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for &swapchain_ptr in &swapchain_src.framebuffers_rw {
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assert_eq!(
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unsafe { &*swapchain_ptr }.as_ptr() as usize % alignment,
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0,
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"the source buffer must be sufficiently aligned to {alignment} bytes for the burst config",
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);
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}
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assert_eq!(
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row_width_bytes % alignment,
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0,
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"the size of a row in bytes must be sufficiently aligned to {alignment} bytes for the burst config",
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);
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assert_eq!(
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row_front_porch_bytes % alignment,
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0,
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"the size of a row's front porch in bytes must be sufficiently aligned to {alignment} bytes for the burst config",
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);
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// We need to make the destination peripheral read the front porch data from somewhere,
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// and that somewhere is currently the bounce buffer.
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// Therefore the front porch must be in bounds.
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assert!(
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row_front_porch_bytes <= window_size,
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"front porch too large"
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);
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let windows_len = swapchain_src.len() / window_size;
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// TODO: Figure out a way to avoid `leak`ing memory.
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// We probably want to store the `Box`es and then unsafely extend the lifetime at sites of usage.
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let bounce_buffer_dst =
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Box::leak(allocate_dma_buffer_in(window_size, burst_config, allocator));
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let bounce_buffer_src =
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Box::leak(allocate_dma_buffer_in(window_size, burst_config, allocator));
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let src_descs = Self::linear_descriptors_for_buffer(window_size, burst_config, |desc| {
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desc.reset_for_tx(desc.next.is_null());
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// Length for TX buffers must be set in software.
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// In RX buffers, it is set by hardware.
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desc.set_length(desc.size());
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});
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let bounce_dst_descs =
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Self::linear_descriptors_for_buffer(window_size, burst_config, |_| {});
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let (bounce_src_descs, descriptors_per_window) = Self::bounce_descriptors_for_buffer(
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windows_len,
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row_front_porch_bytes,
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row_width_bytes,
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window_size_rows,
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unsafe {
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(
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&mut *(bounce_buffer_dst as *mut _),
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&mut *(bounce_buffer_src as *mut _),
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)
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},
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burst_config,
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cyclic,
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);
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Self {
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channel,
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peripheral_src,
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peripheral_dst: Some(peripheral_dst),
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transfer_dst: None,
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burst_config,
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cyclic,
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window_size,
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windows_len,
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swapchain_src,
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bounce_buffer_dst,
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bounce_buffer_src,
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src_descs,
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bounce_dst_descs,
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bounce_src_descs,
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descriptors_per_window,
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window_index_next: 0,
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frame_index_next: 0,
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receiving_transfer: None,
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}
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}
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fn linear_descriptors_for_buffer(
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buffer_len: usize,
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burst_config: BurstConfig,
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mut setup_desc: impl FnMut(&mut DmaDescriptor),
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) -> &'static mut [DmaDescriptor] {
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let max_chunk_size = burst_config.max_compatible_chunk_size();
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let descriptors_len = dma::descriptor_count(buffer_len, max_chunk_size, false);
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// TODO: This leaks memory. Ensure it's only called during setup.
|
||||
let descriptors = Box::leak(vec![DmaDescriptor::EMPTY; descriptors_len].into_boxed_slice());
|
||||
|
||||
// Link up the descriptors.
|
||||
let mut next = core::ptr::null_mut();
|
||||
for desc in descriptors.iter_mut().rev() {
|
||||
desc.next = next;
|
||||
next = desc;
|
||||
}
|
||||
|
||||
// Prepare each descriptor's buffer size.
|
||||
let mut descriptors_it = descriptors.iter_mut();
|
||||
let mut remaining_len = buffer_len;
|
||||
|
||||
while remaining_len > 0 {
|
||||
let chunk_size = core::cmp::min(max_chunk_size, remaining_len);
|
||||
let desc = descriptors_it.next().unwrap();
|
||||
desc.set_size(chunk_size);
|
||||
(setup_desc)(desc);
|
||||
remaining_len -= chunk_size;
|
||||
}
|
||||
|
||||
descriptors
|
||||
}
|
||||
|
||||
fn prepare_descriptors_window(
|
||||
bounce_buffer: &mut [u8],
|
||||
descriptors_window: &mut [DmaDescriptor],
|
||||
row_front_porch_bytes: usize,
|
||||
row_width_bytes: usize,
|
||||
window_size_rows: usize,
|
||||
max_chunk_size: usize,
|
||||
descriptors_per_row: usize,
|
||||
descriptors_per_row_front_porch: usize,
|
||||
) {
|
||||
for (row_index_in_window, descriptors_row) in descriptors_window
|
||||
.chunks_mut(descriptors_per_row)
|
||||
.enumerate()
|
||||
{
|
||||
// let row_index = row_index_in_window + window_index * window_size_rows;
|
||||
let (descriptors_row_front_porch, descriptors_row_stored) =
|
||||
descriptors_row.split_at_mut(descriptors_per_row_front_porch);
|
||||
|
||||
// Prepare front porch descriptors.
|
||||
{
|
||||
let mut descriptors_it = descriptors_row_front_porch.iter_mut();
|
||||
let mut remaining_front_porch = row_front_porch_bytes;
|
||||
|
||||
while remaining_front_porch > 0 {
|
||||
let desc = descriptors_it.next().unwrap();
|
||||
let chunk_size = core::cmp::min(max_chunk_size, remaining_front_porch);
|
||||
remaining_front_porch -= chunk_size;
|
||||
// Just make it point at a bounce buffer.
|
||||
// It is guaranteed to have enough bytes by `DmaBounce::new`.
|
||||
desc.buffer = bounce_buffer.as_mut_ptr();
|
||||
desc.set_size(chunk_size);
|
||||
desc.set_length(chunk_size);
|
||||
desc.reset_for_tx(false);
|
||||
}
|
||||
|
||||
assert!(
|
||||
descriptors_it.next().is_none(),
|
||||
"front porch descriptors must be used up"
|
||||
);
|
||||
assert_eq!(
|
||||
descriptors_row_front_porch
|
||||
.iter()
|
||||
.map(|desc| desc.size())
|
||||
.sum::<usize>(),
|
||||
row_front_porch_bytes
|
||||
);
|
||||
}
|
||||
|
||||
// Prepare window descriptors.
|
||||
{
|
||||
let mut remaining_bounce_buffer =
|
||||
&mut bounce_buffer[row_index_in_window * row_width_bytes..][..row_width_bytes];
|
||||
|
||||
// if remaining_bounce_buffer.len() > row_width_bytes {
|
||||
// remaining_bounce_buffer = &mut remaining_bounce_buffer[..row_width_bytes];
|
||||
// }
|
||||
|
||||
for desc in &mut *descriptors_row_stored {
|
||||
let chunk_size = core::cmp::min(max_chunk_size, remaining_bounce_buffer.len());
|
||||
desc.buffer = remaining_bounce_buffer.as_mut_ptr();
|
||||
remaining_bounce_buffer = &mut remaining_bounce_buffer[chunk_size..];
|
||||
desc.set_size(chunk_size);
|
||||
desc.set_length(chunk_size);
|
||||
desc.reset_for_tx(false);
|
||||
}
|
||||
|
||||
assert!(
|
||||
remaining_bounce_buffer.is_empty(),
|
||||
"bounce buffer must be used up"
|
||||
);
|
||||
assert_eq!(
|
||||
descriptors_row_stored
|
||||
.iter()
|
||||
.map(|desc| desc.size())
|
||||
.sum::<usize>(),
|
||||
row_width_bytes
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
// Set EOF bit on the last descriptor of the window, to signal
|
||||
// that the bounce buffer is done being read from.
|
||||
if let Some(last_desc) = descriptors_window.last_mut() {
|
||||
last_desc.reset_for_tx(true);
|
||||
}
|
||||
|
||||
assert_eq!(
|
||||
descriptors_window
|
||||
.iter()
|
||||
.map(|desc| desc.size())
|
||||
.sum::<usize>(),
|
||||
window_size_rows * (row_front_porch_bytes + row_width_bytes)
|
||||
);
|
||||
}
|
||||
|
||||
fn bounce_descriptors_for_buffer(
|
||||
windows_len: usize,
|
||||
row_front_porch_bytes: usize,
|
||||
row_width_bytes: usize,
|
||||
window_size_rows: usize,
|
||||
bounce_buffers: (&'static mut [u8], &'static mut [u8]),
|
||||
burst_config: BurstConfig,
|
||||
cyclic: bool,
|
||||
) -> (&'static mut [DmaDescriptor], usize) {
|
||||
assert_eq!(
|
||||
bounce_buffers.0.len(),
|
||||
bounce_buffers.1.len(),
|
||||
"bounce buffers must be equal in size"
|
||||
);
|
||||
// If an odd number of windows were needed, two descriptor lists would be needed,
|
||||
assert_eq!(windows_len % 2, 0, "the number of windows must be even");
|
||||
|
||||
let buffer_len = bounce_buffers.0.len();
|
||||
|
||||
assert_eq!(
|
||||
buffer_len,
|
||||
row_width_bytes * window_size_rows,
|
||||
"the provided bounce buffers have an invalid size"
|
||||
);
|
||||
|
||||
// Implementation note:
|
||||
// A cyclic descriptor could consist of just a set of descriptors per window,
|
||||
// so two sets in total, because there are two bounce buffers.
|
||||
// However, we can also access the pointer of the EOF descriptor within the
|
||||
// EOF interrupt handler, which lets us compute which descriptor generated that
|
||||
// interrupt.
|
||||
// This is useful in the case when an interrupt is missed. Then the number of interrupts
|
||||
// handled doesn't correspond to the number of windows sent to the destination peripheral.
|
||||
// In that case, the number of windows sent can be computed from the address of the descriptor.
|
||||
let max_chunk_size = burst_config.max_compatible_chunk_size();
|
||||
let descriptors_per_row_front_porch =
|
||||
dma::descriptor_count(row_front_porch_bytes, max_chunk_size, false);
|
||||
let descriptors_per_row_stored =
|
||||
dma::descriptor_count(row_width_bytes, max_chunk_size, false);
|
||||
let descriptors_per_row = descriptors_per_row_stored + descriptors_per_row_front_porch;
|
||||
let descriptors_per_window = window_size_rows * descriptors_per_row;
|
||||
let descriptors_per_frame = descriptors_per_window * windows_len;
|
||||
let descriptors_frame =
|
||||
Box::leak(vec![DmaDescriptor::EMPTY; descriptors_per_frame].into_boxed_slice());
|
||||
|
||||
// Link up the descriptors.
|
||||
let mut next = if cyclic {
|
||||
descriptors_frame.first_mut().unwrap() as *mut _
|
||||
} else {
|
||||
core::ptr::null_mut()
|
||||
};
|
||||
|
||||
for desc in descriptors_frame.iter_mut().rev() {
|
||||
desc.next = next;
|
||||
next = desc;
|
||||
}
|
||||
|
||||
// Prepare each descriptor's buffer size.
|
||||
let bounce_buffers = [bounce_buffers.0, bounce_buffers.1];
|
||||
|
||||
for (window_index, descriptors_window) in descriptors_frame
|
||||
.chunks_mut(descriptors_per_window)
|
||||
.enumerate()
|
||||
{
|
||||
let bounce_buffer_index = window_index % 2;
|
||||
let bounce_buffer = &mut *bounce_buffers[bounce_buffer_index];
|
||||
|
||||
Self::prepare_descriptors_window(
|
||||
bounce_buffer,
|
||||
descriptors_window,
|
||||
row_front_porch_bytes,
|
||||
row_width_bytes,
|
||||
window_size_rows,
|
||||
max_chunk_size,
|
||||
descriptors_per_row,
|
||||
descriptors_per_row_front_porch,
|
||||
);
|
||||
}
|
||||
|
||||
assert_eq!(
|
||||
descriptors_frame
|
||||
.iter()
|
||||
.map(|desc| desc.size())
|
||||
.sum::<usize>(),
|
||||
windows_len * window_size_rows * (row_front_porch_bytes + row_width_bytes)
|
||||
);
|
||||
|
||||
(descriptors_frame, descriptors_per_window)
|
||||
}
|
||||
|
||||
/// Safety:
|
||||
/// TX descriptors require read access to the buffer.
|
||||
/// RX descriptors require write access to the buffer.
|
||||
unsafe fn linear_descriptors_prepare(
|
||||
descriptors: &mut [DmaDescriptor],
|
||||
mut buffer: Option<&[u8]>,
|
||||
mut setup_desc: impl FnMut(&mut DmaDescriptor),
|
||||
) {
|
||||
for descriptor in descriptors.iter_mut() {
|
||||
if let Some(inner_buffer) = buffer {
|
||||
descriptor.buffer = inner_buffer.as_ptr() as *mut u8;
|
||||
buffer = Some(&inner_buffer[descriptor.size()..]);
|
||||
}
|
||||
(setup_desc)(descriptor);
|
||||
}
|
||||
|
||||
if let Some(buffer) = buffer {
|
||||
assert!(
|
||||
buffer.is_empty(),
|
||||
"a buffer of an incompatible length was assigned to a descriptor set"
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
fn enable_interrupts() {
|
||||
// Enable interrupts for the peripheral, pt. 1.
|
||||
interrupt::enable(
|
||||
INTERRUPT_OUTBOUND,
|
||||
dma_outbound_interrupt_handler.priority(),
|
||||
)
|
||||
.unwrap();
|
||||
|
||||
// Bind the interrupt handler.
|
||||
unsafe {
|
||||
interrupt::bind_interrupt(INTERRUPT_OUTBOUND, dma_outbound_interrupt_handler.handler());
|
||||
}
|
||||
|
||||
// Enable interrupts for the peripheral, pt. 2.
|
||||
DMA::regs()
|
||||
.ch(DMA_CHANNEL_OUTBOUND)
|
||||
.out_int()
|
||||
.ena()
|
||||
.modify(|_, w| w.out_eof().bit(true));
|
||||
}
|
||||
|
||||
/// Receive a window of bytes into the current dst bounce buffer.
|
||||
/// Finally, swaps the bounce buffers.
|
||||
///
|
||||
/// # Safety:
|
||||
/// TODO
|
||||
unsafe fn receive_window_start(&mut self) -> ReceivingTransfer {
|
||||
// Descriptors are initialized by `DmaTxBuf::new`.
|
||||
let buffer_src_window = &self.swapchain_src.get_latest_framebuffer()
|
||||
[self.window_index_next * self.window_size..][..self.window_size];
|
||||
|
||||
unsafe {
|
||||
Self::linear_descriptors_prepare(self.src_descs, Some(buffer_src_window), |_desc| {
|
||||
// No need to call `DmaDescriptor::reset_for_tx`, because
|
||||
// 1. we don't rely on the ownership flag;
|
||||
// 2. the EOF flag is already set during the construction of this buffer.
|
||||
});
|
||||
// TODO: Precompute a descriptor list for each buffer, then use `None` instead of `Some(&mut *self.bounce_buffer_dst)`.
|
||||
Self::linear_descriptors_prepare(
|
||||
self.bounce_dst_descs,
|
||||
Some(self.bounce_buffer_dst),
|
||||
|desc| {
|
||||
desc.reset_for_rx();
|
||||
},
|
||||
);
|
||||
}
|
||||
|
||||
// Extend the lifetime to 'static because it is required by Mem2Mem.
|
||||
//
|
||||
// Safety:
|
||||
// Pointees are done being used by the driver before this scope ends,
|
||||
// this is because we `SimpleMem2MemTransfer::wait()` on the transfer to finish.
|
||||
let bounce_dst_descs: &'static mut [DmaDescriptor] =
|
||||
unsafe { &mut *(self.bounce_dst_descs as *mut _) };
|
||||
let src_descs: &'static mut [DmaDescriptor] = unsafe { &mut *(self.src_descs as *mut _) };
|
||||
|
||||
let mem2mem = unsafe {
|
||||
Mem2Mem::new(
|
||||
self.channel.clone_unchecked(),
|
||||
self.peripheral_src.clone_unchecked(),
|
||||
)
|
||||
}
|
||||
.with_descriptors(bounce_dst_descs, src_descs, self.burst_config)
|
||||
.unwrap();
|
||||
|
||||
ReceivingTransferBuilder {
|
||||
mem2mem,
|
||||
transfer_builder: |mem2mem| {
|
||||
Some(
|
||||
mem2mem
|
||||
.start_transfer(self.bounce_buffer_dst, buffer_src_window)
|
||||
.unwrap(),
|
||||
)
|
||||
},
|
||||
}
|
||||
.build()
|
||||
}
|
||||
|
||||
/// Receive a window of bytes into the current dst bounce buffer.
|
||||
/// Finally, swaps the bounce buffers.
|
||||
async fn receive_window(&mut self) {
|
||||
// Descriptors are initialized by `DmaTxBuf::new`.
|
||||
let buffer_src_window = &self.swapchain_src.get_latest_framebuffer()
|
||||
[self.window_index_next * self.window_size..][..self.window_size];
|
||||
|
||||
unsafe {
|
||||
Self::linear_descriptors_prepare(self.src_descs, Some(buffer_src_window), |_desc| {
|
||||
// No need to call `DmaDescriptor::reset_for_tx`, because
|
||||
// 1. we don't rely on the ownership flag;
|
||||
// 2. the EOF flag is already set during the construction of this buffer.
|
||||
});
|
||||
// TODO: Precompute a descriptor list for each buffer, then use `None` instead of `Some(&mut *self.bounce_buffer_dst)`.
|
||||
Self::linear_descriptors_prepare(
|
||||
self.bounce_dst_descs,
|
||||
Some(self.bounce_buffer_dst),
|
||||
|desc| {
|
||||
desc.reset_for_rx();
|
||||
},
|
||||
);
|
||||
}
|
||||
|
||||
{
|
||||
// Extend the lifetime to 'static because it is required by Mem2Mem.
|
||||
//
|
||||
// Safety:
|
||||
// Pointees are done being used by the driver before this scope ends,
|
||||
// this is because we `SimpleMem2MemTransfer::wait()` on the transfer to finish.
|
||||
let bounce_dst_descs: &'static mut [DmaDescriptor] =
|
||||
unsafe { &mut *(self.bounce_dst_descs as *mut _) };
|
||||
let src_descs: &'static mut [DmaDescriptor] =
|
||||
unsafe { &mut *(self.src_descs as *mut _) };
|
||||
|
||||
let mut mem2mem = Mem2Mem::new(self.channel.reborrow(), self.peripheral_src.reborrow())
|
||||
.into_async()
|
||||
.with_descriptors(bounce_dst_descs, src_descs, self.burst_config)
|
||||
.unwrap();
|
||||
let transfer = mem2mem
|
||||
.start_transfer(self.bounce_buffer_dst, buffer_src_window)
|
||||
.unwrap();
|
||||
|
||||
transfer.wait_async().await.unwrap();
|
||||
}
|
||||
|
||||
self.increase_window_counter(1);
|
||||
}
|
||||
|
||||
fn increase_window_counter(&mut self, windows: isize) {
|
||||
if windows.rem_euclid(2) == 1 {
|
||||
core::mem::swap(&mut self.bounce_buffer_dst, &mut self.bounce_buffer_src);
|
||||
}
|
||||
|
||||
let window_index_next = self.window_index_next as isize + windows;
|
||||
self.frame_index_next = (self.frame_index_next as isize
|
||||
+ window_index_next / self.windows_len as isize)
|
||||
as usize;
|
||||
self.window_index_next = window_index_next.rem_euclid(self.windows_len as isize) as usize;
|
||||
}
|
||||
|
||||
pub async fn launch_interrupt_driven_task(mut self) {
|
||||
Self::enable_interrupts();
|
||||
|
||||
// Receive the first 2 windows, so that the outbound transfer can read valid data.
|
||||
self.receive_window().await;
|
||||
|
||||
let dma_tx_buffer = self.get_dma_tx_buffer();
|
||||
let transfer = self
|
||||
.peripheral_dst
|
||||
.take()
|
||||
.unwrap()
|
||||
.send(self.cyclic /* Send perpetually */, dma_tx_buffer)
|
||||
.unwrap_or_else(|(error, _, _)| {
|
||||
panic!("failed to begin the transmission of the first frame: {error:?}");
|
||||
});
|
||||
self.transfer_dst = Some(transfer);
|
||||
self.receiving_transfer = Some(unsafe { self.receive_window_start() });
|
||||
|
||||
unsafe {
|
||||
*DMA_STATE.0.get() = Some(self);
|
||||
}
|
||||
}
|
||||
|
||||
fn get_dma_tx_buffer(&mut self) -> DmaTxBounceBuf {
|
||||
DmaTxBounceBuf {
|
||||
preparation: dma::Preparation {
|
||||
start: self.bounce_src_descs.first_mut().unwrap(),
|
||||
direction: dma::TransferDirection::Out,
|
||||
accesses_psram: false,
|
||||
burst_transfer: self.burst_config,
|
||||
// We don't care about ownership.
|
||||
// Just yeet whatever the descriptors point to to the destination peripheral.
|
||||
check_owner: Some(false),
|
||||
auto_write_back: false,
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct DmaTxBounceBuf {
|
||||
preparation: dma::Preparation,
|
||||
}
|
||||
|
||||
unsafe impl DmaTxBuffer for DmaTxBounceBuf {
|
||||
type View = Self;
|
||||
type Final = Self;
|
||||
|
||||
fn prepare(&mut self) -> dma::Preparation {
|
||||
dma::Preparation {
|
||||
start: self.preparation.start,
|
||||
direction: self.preparation.direction,
|
||||
accesses_psram: self.preparation.accesses_psram,
|
||||
burst_transfer: self.preparation.burst_transfer,
|
||||
check_owner: self.preparation.check_owner,
|
||||
auto_write_back: self.preparation.auto_write_back,
|
||||
}
|
||||
}
|
||||
|
||||
fn into_view(self) -> Self::View {
|
||||
self
|
||||
}
|
||||
|
||||
fn from_view(view: Self::View) -> Self::Final {
|
||||
view
|
||||
}
|
||||
}
|
||||
|
||||
static DMA_STATE: SyncUnsafeCell<Option<DmaBounce>> = SyncUnsafeCell(UnsafeCell::new(None));
|
||||
|
||||
#[repr(transparent)]
|
||||
pub struct SyncUnsafeCell<T>(UnsafeCell<T>);
|
||||
|
||||
unsafe impl<T> Sync for SyncUnsafeCell<T> {}
|
||||
|
||||
#[handler(priority = Priority::Priority3)]
|
||||
#[ram] // Improves performance.
|
||||
fn dma_outbound_interrupt_handler() {
|
||||
let interrupt = DMA::regs().ch(DMA_CHANNEL_OUTBOUND).out_int();
|
||||
let bounce_buffer_sent = interrupt.st().read().out_eof().bit_is_set();
|
||||
|
||||
if !bounce_buffer_sent {
|
||||
return;
|
||||
}
|
||||
|
||||
// Clear the bit by writing 1 to the clear bits.
|
||||
interrupt.clr().write(|w| w.out_eof().bit(true));
|
||||
|
||||
// SAFETY: This value is only ever read in our interrupt handler,
|
||||
// and interrupts are disabled, and we only use this in one thread.
|
||||
let Some(dma_state) = unsafe { &mut *DMA_STATE.0.get() }.as_mut() else {
|
||||
error!("no DMA state available when executing DMA interrupt handler");
|
||||
return;
|
||||
};
|
||||
|
||||
// The descriptor of the buffer with an EOF flag that just finished being sent.
|
||||
let descriptor_ptr = DMA::regs()
|
||||
.ch(DMA_CHANNEL_OUTBOUND)
|
||||
.out_eof_des_addr()
|
||||
.read()
|
||||
.out_eof_des_addr()
|
||||
.bits() as *const DmaDescriptor;
|
||||
// This is the index of the window that just finished being transmitted to the destination peripheral.
|
||||
let window_sent_index =
|
||||
unsafe { descriptor_ptr.offset_from_unsigned(dma_state.bounce_src_descs.as_ptr()) }
|
||||
/ dma_state.descriptors_per_window;
|
||||
// The next window to be sent is `(window_sent_index + 1) % dma_state.windows_len`.
|
||||
// That is not the window we want to buffer, because the transmissions would race.
|
||||
// We instead want to buffer the next window:
|
||||
let window_index_next = (window_sent_index + 2) % dma_state.windows_len;
|
||||
|
||||
// Swap bounce buffers.
|
||||
if (dma_state.windows_len + window_index_next - dma_state.window_index_next) % 2 == 1 {
|
||||
core::mem::swap(
|
||||
&mut dma_state.bounce_buffer_dst,
|
||||
&mut dma_state.bounce_buffer_src,
|
||||
);
|
||||
}
|
||||
|
||||
dma_state.window_index_next = window_index_next;
|
||||
|
||||
let mut receiving_transfer = dma_state
|
||||
.receiving_transfer
|
||||
.take()
|
||||
.expect("no ongoing transfer to a bounce buffer present");
|
||||
let receiving_transfer = receiving_transfer
|
||||
.with_mut(|x| x.transfer.take())
|
||||
.expect("no ongoing inner transfer to a bounce buffer present");
|
||||
|
||||
if receiving_transfer.is_done() {
|
||||
drop(receiving_transfer);
|
||||
} else {
|
||||
// error!("the transfer to a bounce buffer has not finished yet, waiting");
|
||||
receiving_transfer.wait().unwrap();
|
||||
}
|
||||
|
||||
// If there is any ongoing transfer, cancel it and start a new one.
|
||||
dma_state.receiving_transfer = Some(unsafe { dma_state.receive_window_start() });
|
||||
}
|
||||
|
||||
// #[handler(priority = Priority::Priority3)]
|
||||
// #[ram] // Improves performance.
|
||||
// fn dma_inbound_interrupt_handler() {
|
||||
// warn!("Inbound");
|
||||
|
||||
// let interrupt = DMA::regs().ch(DMA_CHANNEL_INBOUND).in_int();
|
||||
// let bounce_buffer_processed = interrupt.st().read().in_done().bit_is_set();
|
||||
// if bounce_buffer_processed {
|
||||
// // Clear the bit by writing 1 to the clear bits.
|
||||
// interrupt.clr().write(|w| w.in_done().bit(true));
|
||||
|
||||
// assert!(
|
||||
// !INBOUND_TRANSFER_FINISHED.signaled(),
|
||||
// "inbound transfer already signalled"
|
||||
// );
|
||||
// INBOUND_TRANSFER_FINISHED.signal(());
|
||||
// }
|
||||
// }
|
||||
|
||||
// pub async fn run_lcd(
|
||||
// mut st7701s: St7701s<'static, Blocking>,
|
||||
// framebuffer: &'static mut Framebuffer,
|
||||
// ) {
|
||||
// loop {
|
||||
// // Timer::after(Duration::from_millis(100)).await;
|
||||
// // yield_now().await;
|
||||
// SIGNAL_LCD_SUBMIT.wait().await;
|
||||
|
||||
// // TODO: Use bounce buffers:
|
||||
// // https://docs.espressif.com/projects/esp-idf/en/v5.0/esp32s3/api-reference/peripherals/lcd.html#bounce-buffer-with-single-psram-frame-buffer
|
||||
// // This can be implemented as a `DmaTxBuffer`.
|
||||
// let transfer = match st7701s.dpi.send(false, framebuffer.dma_buf.take().unwrap()) {
|
||||
// Err((error, result_dpi, result_dma_buf)) => {
|
||||
// error!(
|
||||
// "An error occurred while initiating transfer of the framebuffer to the LCD display: {error:?}"
|
||||
// );
|
||||
// st7701s.dpi = result_dpi;
|
||||
// framebuffer.dma_buf = Some(result_dma_buf);
|
||||
// continue;
|
||||
// }
|
||||
// Ok(transfer) => transfer,
|
||||
// };
|
||||
|
||||
// // This could be used to allow other tasks to be executed on the first core, but that causes
|
||||
// // the flash to be accessed, which interferes with the framebuffer transfer.
|
||||
// // For that reason, it is disabled, and this task blocks the first core, until the transfer
|
||||
// // is complete.
|
||||
// #[cfg(not(feature = "limit-fps"))]
|
||||
// while !transfer.is_done() {
|
||||
// // Timer::after_millis(1).await;
|
||||
// rmk::embassy_futures::yield_now().await;
|
||||
// }
|
||||
|
||||
// let result;
|
||||
// let dma_buf;
|
||||
// (result, st7701s.dpi, dma_buf) = transfer.wait();
|
||||
// framebuffer.dma_buf = Some(dma_buf);
|
||||
|
||||
// SIGNAL_UI_RENDER.signal(());
|
||||
|
||||
// if let Err(error) = result {
|
||||
// error!(
|
||||
// "An error occurred while transferring framebuffer to the LCD display: {error:?}"
|
||||
// );
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
|
||||
/// Allocates a buffer appropriately aligned for use with DMA.
|
||||
pub fn allocate_dma_buffer_in<A: Allocator>(
|
||||
len: usize,
|
||||
burst_config: BurstConfig,
|
||||
alloc: A,
|
||||
) -> Box<[u8], A> {
|
||||
// Conservative alignment. Maxiumum of the cartesian product of [tx, rx] × [internal, external].
|
||||
let alignment = burst_config.min_compatible_alignment();
|
||||
|
||||
assert_eq!(
|
||||
len % alignment,
|
||||
0,
|
||||
"the size of a DMA buffer must be a multiple of {alignment} bytes, but it is {len} bytes large"
|
||||
);
|
||||
|
||||
// ⚠️ Note: For chips that support DMA to/from PSRAM (ESP32-S3) DMA transfers to/from PSRAM
|
||||
// have extra alignment requirements. The address and size of the buffer pointed to by each
|
||||
// descriptor must be a multiple of the cache line (block) size. This is 32 bytes on ESP32-S3.
|
||||
// That is ensured by the `assert_eq` preceding this block.
|
||||
unsafe {
|
||||
let raw = alloc
|
||||
.allocate_zeroed(Layout::from_size_align(len, alignment).unwrap())
|
||||
.expect("failed to allocate a DMA buffer");
|
||||
Box::from_raw_in(raw.as_ptr(), alloc)
|
||||
}
|
||||
}
|
||||
|
||||
// TODO: Rename or get rid of.
|
||||
pub struct Framebuffer {
|
||||
pub width: u32,
|
||||
|
|
|
|||
Loading…
Reference in a new issue