From b4b2d5be8eeb31bf88c81098f111afb5e2c5a138 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jakub=20Hlusi=C4=8Dka?= Date: Tue, 29 Jul 2025 01:34:19 +0200 Subject: [PATCH] init --- .gitignore | 32 + README.md | 16 + acid.kicad_dru | 133 + acid.kicad_pcb | 43254 ++++++++++++++++++++++++++++++++++++++ acid.kicad_pro | 657 + acid.kicad_sch | 1953 ++ matrix_switch.kicad_sch | 12002 +++++++++++ 7 files changed, 58047 insertions(+) create mode 100644 .gitignore create mode 100644 README.md create mode 100644 acid.kicad_dru create mode 100644 acid.kicad_pcb create mode 100644 acid.kicad_pro create mode 100644 acid.kicad_sch create mode 100644 matrix_switch.kicad_sch diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..e80bb0f --- /dev/null +++ b/.gitignore @@ -0,0 +1,32 @@ +# For PCBs designed using KiCad: http://www.kicad-pcb.org/ +# Format documentation: http://kicad-pcb.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*.kicad_prl +*.sch-bak +*~ +_autosave-* +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache +/build + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv + +# Backups +acid-backups diff --git a/README.md b/README.md new file mode 100644 index 0000000..9f2671e --- /dev/null +++ b/README.md @@ -0,0 +1,16 @@ +# Advanced Clicky Input Device (ACID) + +Schematics and design files for a DIY keyboard. + +## Goals + +- A Preonic-like 12x5 ortholinear layout +- A powerful microcontroller (ESP32-S3 or similar) +- Lots of flash memory +- An RGB screen + +## Dependencies + +- [UnexpectedMaker's esp32s3](https://github.com/UnexpectedMaker/esp32s3) +- [KiCad-DesignRules](https://github.com/labtroll/KiCad-DesignRules) +- [MX_V2 switch footprints](https://github.com/ai03-2725/MX_V2) diff --git a/acid.kicad_dru b/acid.kicad_dru new file mode 100644 index 0000000..c42eb3c --- /dev/null +++ b/acid.kicad_dru @@ -0,0 +1,133 @@ +(version 1) +# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '.kicad_dru' file). +# +# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities +# +# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules +# +# Inspiration +# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments) +# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments) + +# TODO new rule: NPTH pads. +# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter. +# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)." + +# TODO: new rule for plated slots: min diameter/width 0.5mm +# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad." + +# TODO new rule: non-plated slots: min diameter/width 1.0mm +# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)"" + +(rule "Track width, outer layer (1oz copper)" + (layer outer) + (condition "A.Type == 'track'") + (constraint track_width (min 0.127mm)) +) + +(rule "Track spacing, outer layer (1oz copper)" + (layer outer) + (condition "A.Type == 'track' && B.Type == A.Type") + (constraint clearance (min 0.127mm)) +) + +(rule "Track width, inner layer" + (layer inner) + (condition "A.Type == 'track'") + (constraint track_width (min 0.09mm)) +) + +(rule "Track spacing, inner layer" + (layer inner) + (condition "A.Type == 'track' && B.Type == A.Type") + (constraint clearance (min 0.09mm)) +) + +(rule "Silkscreen text" + (layer "?.Silkscreen") + (condition "A.Type == 'Text' || A.Type == 'Text Box'") + (constraint text_thickness (min 0.15mm)) + (constraint text_height (min 1mm)) +) + +(rule "Pad to Silkscreen" + (layer outer) + (condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'") + (constraint silk_clearance (min 0.15mm)) +) + +(rule "Edge (routed) to track clearance" + (condition "A.Type == 'track'") + (constraint edge_clearance (min 0.3mm)) +) + +#(rule "Edge (v-cut) to track clearance" +# (condition "A.Type == 'track'") +# (constraint edge_clearance (min 0.4mm)) +#) + +# JLCPCB restrictions ambiguous: +# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)" +# This rule handles diameter minimum and maximum for ALL holes. +# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) +(rule "Hole diameter" + (constraint hole_size (min 0.2mm) (max 6.3mm)) +) + +(rule "Hole (NPTH) diameter" + (layer outer) + (condition "!A.isPlated()") + (constraint hole_size (min 0.5mm)) +) + +# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm +(rule "Hole (castellated) diameter" + (layer outer) + (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'") + (constraint hole_size (min 0.6mm)) +) + +# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions) +# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production." +(rule "Annular ring width (via and PTH)" + (layer outer) + (condition "A.isPlated()") + (constraint annular_width (min 0.075mm)) +) + +(rule "Clearance: hole to hole (perimeter), different nets" + (layer outer) + (condition "A.Net != B.Net") + (constraint hole_to_hole (min 0.5mm)) +) + +(rule "Clearance: hole to hole (perimeter), same net" + (layer outer) + (condition "A.Net == B.Net") + (constraint hole_to_hole (min 0.254mm)) +) + +(rule "Clearance: track to NPTH hole (perimeter)" +# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net") + (condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net") + (constraint hole_clearance (min 0.254mm)) +) + +(rule "Clearance: track to PTH hole perimeter" + (condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net") + (constraint hole_clearance (min 0.33mm)) +) + +# TODO: try combining with rule "Clearance: PTH to track, different nets" +(rule "Clearance: track to pad" + (condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net") + (constraint clearance (min 0.2mm)) +) + +(rule "Clearance: pad/via to pad/via" + (layer outer) +# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net") + (condition "A.isPlated() && B.isPlated() && A.Net != B.Net") + (constraint clearance (min 0.127mm)) +) + diff --git a/acid.kicad_pcb b/acid.kicad_pcb new file mode 100644 index 0000000..f31c461 --- /dev/null +++ b/acid.kicad_pcb @@ -0,0 +1,43254 @@ +(kicad_pcb + (version 20241229) + (generator "pcbnew") + (generator_version "9.0") + (general + (thickness 1.6) + (legacy_teardrops no) + ) + (paper "A4") + (layers + (0 "F.Cu" signal) + (4 "In1.Cu" signal) + (6 "In2.Cu" signal) + (2 "B.Cu" signal) + (9 "F.Adhes" user "F.Adhesive") + (11 "B.Adhes" user "B.Adhesive") + (13 "F.Paste" user) + (15 "B.Paste" user) + (5 "F.SilkS" user "F.Silkscreen") + (7 "B.SilkS" user "B.Silkscreen") + (1 "F.Mask" user) + (3 "B.Mask" user) + (17 "Dwgs.User" user "User.Drawings") + (19 "Cmts.User" user "User.Comments") + (21 "Eco1.User" user "User.Eco1") + (23 "Eco2.User" user "User.Eco2") + (25 "Edge.Cuts" user) + (27 "Margin" user) + (31 "F.CrtYd" user "F.Courtyard") + (29 "B.CrtYd" user "B.Courtyard") + (35 "F.Fab" user) + (33 "B.Fab" user) + (39 "User.1" user) + (41 "User.2" user) + (43 "User.3" user) + (45 "User.4" user) + (47 "User.5" user) + (49 "User.6" user) + (51 "User.7" user) + (53 "User.8" user) + (55 "User.9" user) + ) + (setup + (stackup + (layer "F.SilkS" + (type "Top Silk Screen") + ) + (layer "F.Paste" + (type "Top Solder Paste") + ) + (layer "F.Mask" + (type "Top Solder Mask") + (thickness 0.01) + ) + (layer "F.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 1" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In1.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 2" + (type "core") + (thickness 1.24) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "In2.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "dielectric 3" + (type "prepreg") + (thickness 0.1) + (material "FR4") + (epsilon_r 4.5) + (loss_tangent 0.02) + ) + (layer "B.Cu" + (type "copper") + (thickness 0.035) + ) + (layer "B.Mask" + (type "Bottom Solder Mask") + (thickness 0.01) + ) + (layer "B.Paste" + (type "Bottom Solder Paste") + ) + (layer "B.SilkS" + (type "Bottom Silk Screen") + ) + (copper_finish "HAL lead-free") + (dielectric_constraints no) + ) + (pad_to_mask_clearance 0) + (allow_soldermask_bridges_in_footprints no) + (tenting front back) + (pcbplotparams + (layerselection 0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 0 "") + (net 1 "Net-(D_{0,0}1-A)") + (net 2 "Row_{0}") + (net 3 "Net-(D_{0,1}1-A)") + (net 4 "Net-(D_{0,2}1-A)") + (net 5 "Net-(D_{0,3}1-A)") + (net 6 "Net-(D_{0,4}1-A)") + (net 7 "Net-(D_{0,5}1-A)") + (net 8 "Net-(D_{0,6}1-A)") + (net 9 "Net-(D_{0,7}1-A)") + (net 10 "Net-(D_{0,8}1-A)") + (net 11 "Net-(D_{0,9}1-A)") + (net 12 "Net-(D_{0,10}1-A)") + (net 13 "Net-(D_{0,11}1-A)") + (net 14 "Net-(D_{1,0}1-A)") + (net 15 "Row_{1}") + (net 16 "Net-(D_{1,1}1-A)") + (net 17 "Net-(D_{1,2}1-A)") + (net 18 "Net-(D_{1,3}1-A)") + (net 19 "Net-(D_{1,4}1-A)") + (net 20 "Net-(D_{1,5}1-A)") + (net 21 "Net-(D_{1,6}1-A)") + (net 22 "Net-(D_{1,7}1-A)") + (net 23 "Net-(D_{1,8}1-A)") + (net 24 "Net-(D_{1,9}1-A)") + (net 25 "Net-(D_{1,10}1-A)") + (net 26 "Net-(D_{1,11}1-A)") + (net 27 "Net-(D_{2,0}1-A)") + (net 28 "Row_{2}") + (net 29 "Net-(D_{2,1}1-A)") + (net 30 "Net-(D_{2,2}1-A)") + (net 31 "Net-(D_{2,3}1-A)") + (net 32 "Net-(D_{2,4}1-A)") + (net 33 "Net-(D_{2,5}1-A)") + (net 34 "Net-(D_{2,6}1-A)") + (net 35 "Net-(D_{2,7}1-A)") + (net 36 "Net-(D_{2,8}1-A)") + (net 37 "Net-(D_{2,9}1-A)") + (net 38 "Net-(D_{2,10}1-A)") + (net 39 "Net-(D_{2,11}1-A)") + (net 40 "Row_{3}") + (net 41 "Net-(D_{3,0}1-A)") + (net 42 "Net-(D_{3,1}1-A)") + (net 43 "Net-(D_{3,2}1-A)") + (net 44 "Net-(D_{3,3}1-A)") + (net 45 "Net-(D_{3,4}1-A)") + (net 46 "Net-(D_{3,5}1-A)") + (net 47 "Net-(D_{3,6}1-A)") + (net 48 "Net-(D_{3,7}1-A)") + (net 49 "Net-(D_{3,8}1-A)") + (net 50 "Net-(D_{3,9}1-A)") + (net 51 "Net-(D_{3,10}1-A)") + (net 52 "Net-(D_{3,11}1-A)") + (net 53 "Row_{4}") + (net 54 "Net-(D_{4,0}1-A)") + (net 55 "Net-(D_{4,1}1-A)") + (net 56 "Net-(D_{4,2}1-A)") + (net 57 "Net-(D_{4,3}1-A)") + (net 58 "Net-(D_{4,4}1-A)") + (net 59 "Net-(D_{4,5}1-A)") + (net 60 "Net-(D_{4,6}1-A)") + (net 61 "Net-(D_{4,7}1-A)") + (net 62 "Net-(D_{4,8}1-A)") + (net 63 "Net-(D_{4,9}1-A)") + (net 64 "Net-(D_{4,10}1-A)") + (net 65 "Net-(D_{4,11}1-A)") + (net 66 "Col_{0}") + (net 67 "Col_{1}") + (net 68 "Col_{2}") + (net 69 "Col_{3}") + (net 70 "Col_{4}") + (net 71 "Col_{5}") + (net 72 "Col_{6}") + (net 73 "Col_{7}") + (net 74 "Col_{8}") + (net 75 "Col_{9}") + (net 76 "Col_{10}") + (net 77 "Col_{11}") + (net 78 "unconnected-(U1-VBAT-Pad1)") + (net 79 "unconnected-(U1-5V-Pad3)") + (net 80 "GND") + (net 81 "unconnected-(U1-RX-Pad23)") + (net 82 "unconnected-(U1-IO7-Pad28)") + (net 83 "unconnected-(U1-LDO2_OUT-Pad12)") + (net 84 "unconnected-(U1-IO36-Pad32)") + (net 85 "unconnected-(U1-TX-Pad24)") + (net 86 "unconnected-(U1-IO37-Pad33)") + (net 87 "unconnected-(U1-IO34-Pad31)") + (net 88 "unconnected-(U1-IO8-Pad29)") + (net 89 "unconnected-(U1-IO9-Pad30)") + (net 90 "unconnected-(U1-IO35-Pad34)") + (net 91 "unconnected-(U1-IO6-Pad27)") + (net 92 "unconnected-(U1-3V3-Pad4)") + (footprint "Diode_SMD:D_MiniMELF" + (layer "F.Cu") + (uuid "0339ec7d-3474-4e5e-b5e4-c6c7f179aefa") + (at 182.11 -33.035) + (descr "Diode Mini-MELF (SOD-80)") + (tags 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