Jakub Hlusička
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2e69cea11c
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rev 1
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2025-08-14 03:02:10 +02:00 |
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Jakub Hlusička
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42a6c51ba4
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Add an image to the PCB
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2025-08-14 02:24:22 +02:00 |
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Jakub Hlusička
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45c51ab3e0
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Add a missing 3D model for the FPC connector
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2025-08-14 02:13:43 +02:00 |
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Jakub Hlusička
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991e82c00a
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Silkscreen improvements
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2025-08-14 02:03:59 +02:00 |
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Jakub Hlusička
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bf59be36b9
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Resolve DRC messages on the PCB
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2025-08-14 01:23:56 +02:00 |
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Jakub Hlusička
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85a86ee89c
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WIP manual routing 3
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2025-08-14 01:01:07 +02:00 |
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Jakub Hlusička
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a745417b3e
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WIP manual routing 2
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2025-08-13 21:31:14 +02:00 |
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Jakub Hlusička
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cf5c0188af
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WIP manual routing
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2025-08-13 02:26:53 +02:00 |
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Jakub Hlusička
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25691c4e82
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WIP
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2025-08-12 20:49:39 +02:00 |
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Jakub Hlusička
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da6e19eb73
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Manual routing
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2025-08-12 03:55:15 +02:00 |
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Jakub Hlusička
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c020218105
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WIP
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2025-08-12 03:29:25 +02:00 |
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Jakub Hlusička
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14795ac33f
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Component layout
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2025-08-12 02:31:54 +02:00 |
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Jakub Hlusička
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ebc0113d26
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Attempt to manually route traces
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2025-08-12 00:13:00 +02:00 |
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Jakub Hlusička
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e8c7a379ef
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Add screw holes
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2025-08-11 02:52:40 +02:00 |
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Jakub Hlusička
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f33a692be1
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Design a basic enclosure
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2025-08-10 02:05:16 +02:00 |
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Jakub Hlusička
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5d44e6b425
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Add a spacebar switch
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2025-08-06 05:03:17 +02:00 |
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Jakub Hlusička
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7980e0386e
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Fix CS with a pull-down resistor rather than a pull-up
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2025-08-05 14:29:07 +02:00 |
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Jakub Hlusička
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d39fc3f6f2
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Begin PCB layout
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2025-08-05 03:12:42 +02:00 |
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Jakub Hlusička
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0ba621b9be
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Before adding IO expanders
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2025-08-01 00:38:10 +02:00 |
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Jakub Hlusička
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b4b2d5be8e
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init
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2025-07-29 01:34:19 +02:00 |
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